Towards fog-driven IoT eHealth:Promises and challenges of IoT in medicine and healthcare

Internet of Things (IoT) offers a seamless platform to connect people and objects to one another for enriching and making our lives easier. This vision carries us from compute-based centralized schemes to a more distributed environment offering a vast amount of applications such as smart wearables, smart home, smart mobility, and smart cities. In this paper we discuss applicability of IoT in healthcare and medicine by presenting a holistic architecture of IoT eHealth ecosystem. Healthcare is becoming increasingly difficult to manage due to insufficient and less effective healthcare services to meet the increasing demands of rising aging population with chronic diseases. We propose that this requires a transition from the clinic-centric treatment to patient-centric healthcare where each agent such as hospital, patient, and services are seamlessly connected to each other. This patient-centric IoT eHealth ecosystem needs a multi-layer architecture: (1) device, (2) fog computing and (3) cloud to empower handling of complex data in terms of its variety, speed, and latency. This fog-driven IoT architecture is followed by various case examples of services and applications that are implemented on those layers. Those examples range from mobile health, assisted living, e-medicine, implants, early warning systems, to population monitoring in smart cities. We then finally address the challenges of IoT eHealth such as data management, scalability, regulations, interoperability, device–network–human interfaces, security, and privacy

Clock Tree Optimization in Synchronous CMOS Digital Circuits for Substrate Noise Reduction Using Folding of Supply Current Transients

In a synchronous clock distribution network with zero latencies, digital circuits switch simultaneously on the clock edge, therefore they generate substrate noise due to the sharp peaks on the supply current. We present a novel methodology optimizing the clock tree for less substrate generation by using statistical single cycle supply current profiles computed for every clock region taking the timing constraints into account. Our methodology is novel as it uses an error-driven compressed data set during the optimization over a number of clock regions specified for a significant reduction in substrate noise. It also produces a quality analysis of the computed latencies as a function of the clock skew. The experimental results show >x2 reduction of substrate noise generation from the circuits having four clock regions of which the latencies are optimized

A Cascadable Random Neural Network Chip with Reconfigurable Topology

A digital integrated circuit (IC) is realized using the random neural network (RNN) model introduced by Gelenbe. The RNN IC employs both configurable routing and random signaling. In this paper we present the networking/routing aspects as well as the performance results of an RNN network implemented by the RNN IC. In the RNN model, each neuron accumulates arriving signals and can fire if its potential at a given instant of time is strictly positive. Firing occurs at random, the intervals between successive firing instants following an exponential distribution of constant rate. When a neuron fires, it routes the generated pulses to the output lines in accordance with the connection probabilities. The number of neurons in the network is programmable and could be connected to each other with any desired neuron interconnection and this connection could be changed on the fly. The RNN chip architecture is cascadable to generate any network topology. All the parts of the RNN circuit are implemented using a standard digital Complimentary-Metal-Oxide-Semiconductor (CMOS) process

Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling

<p/> <p>Ultra-wideband (UWB) impulse radios show strong advantages for the implementation of low-power transceivers. In this paper, we analyze the impact of CMOS technology scaling on power consumption of UWB impulse radios. It is shown that the power consumption of the synchronization constitutes a large portion of the total power in the receiver. A traditional technique to reduce the power consumption at the receiver is to operate the UWB radios with a very low duty cycle on an architecture with extreme parallelism. On the other hand, this requires more silicon area and this is limited by the leakage power consumption, which becomes more and more a problem in future CMOS technologies. The proposed quantitative framework allows systematic use of digital low-power design techniques in future UWB transceivers.</p